Programmable Resistive Device (PRD) can be programmed into different resistance states and can retain data when the power supply of a memory is cut off. The memory can be used to permanent store data such as parameters, configuration settings, long-term data storage, etc. Similarly, this kind of memory can be used to store instructions, or codes, for microprocessors, Digital Signal Processors (DSPs), or microcontrollers (MCU), etc. PRD memory has three operations, read, write (or called program), and erase, for reading data, programming data, and erasing data before re-programming. PRD memory can be an EPROM, EEPROM, or flash memory that can be programmed from 10K to 100K times, or Multiple-Time Programmable (MTP) to be programmed from a few times to a few hundred times, or One-Time Programmable (OTP) to be programmed one time only. The PRD memory can also be emerging memories such as PCRAM (Phase Change RAM), RRAM (Resistive RAM), FRAM (Ferroelectric RAM), or MRAM (Magnetic RAM) that has at least one Magnetic Tunnel Junction (MTJ) in the cell.
One-Time-Programmable (OTP) is a particular type of PRD memory that can be programmed only once. An OTP memory allows the memory cells being programmed once and only once in their lifetime. OTP is generally based on standard CMOS processes and is usually embedded into an integrated circuit that allows each die in a wafer to be customized. There are many applications for OTP, such as memory repair, device trimming, configuration parameters, chip ID, security key, feature select, and PROM, etc.
FIG. 1 shows a conventional low-bit-count OTP memory 6. The OTP memory 6 has a shared pin 7 and a plurality of OTP cells that has a program pad 8 and an OTP element 5 for each cell. The OTP element is usually an electrical fuse that is fabricated from polysilicon, silicided polysilicon, or metal in CMOS processes. To program a fuse, a high voltage can be applied between the pad 8 and pad 7 to conduct a high current flowing through the OTP element 5 to break the fuse into a high resistance state. In 0.35 um CMOS, programming a polycide (i.e. polysilicon with silicide on top) fuse takes about 60 mA for 100 millisecond. The program current is so high that the other fuses in shared pins or the nearby interlayer dielectric can be damaged. The area for a one-pad-one-fuse OTP cell is also very large, about 150 um2, especially for low-pin-count chips.
FIG. 2(a) shows another conventional PRD cell 10. The PRD cell 10 has a PRD element 11 and a program selector 12. The PRD element 11 is coupled to a supply voltage V+ in one end and to a program selector 12 in the other end. The program selector 12 has the other end coupled to a second supply voltage V−. The program selector 12 can be turned on by asserting a control terminal Sel. The program selector 12 is usually constructed from a MOS device. The NVM element 11 is usually an electrical fuse based on polysilicon, silicided polysilicon, metal, a floating gate to store charges, or an anti-fuse based on gate oxide breakdown, etc.
FIG. 2(b) shows a PRD cell 15 using a diode as program selector, which is well suited for a low-bit-count PRD. The PRD cell 15 has a PRD element 16 and a diode as a program selector 17. The PRD element 16 is coupled to a supply voltage V+ in one end and a program selector 17 in the other. The program selector 17 has the other end coupled to a second supply voltage V− as a select signal Sel. It is very desirable for the program selector 17 being fabricated in CMOS compatible processes. The program selector 17 can be constructed from a diode that can be embodied as a junction diode with at least one P+ active region on an N well, or a diode with P+ and N+ implants on two ends of a polysilicon substrate or active region on an insulated substrate. The PRD element 16 is commonly an electrical fuse based on polysilicon, silicided polysilicon, metal, CMOS gate material, or anti-fuse based on gate oxide breakdown.
FIG. 3 shows a portion of a block diagram of a 1K×8 PRD memory 50 that has a memory array 51, X-decoders 52, Y-decoder 53, sense amplifiers 54, output latch 55, output multiplexer (MUX) 56, and control logic 57. The PRD memory cells depending on a floating-gate to store charges or rupture the oxide to create different logic state are very hard to fabricate and sensitive to process variation that require high voltage to program. Therefore, there are some high voltage circuits and charge pumps in the peripherals. These kinds of PRD memory need custom design, which is very time consuming and costly.
Conventional architecture, logic, and circuit designs for PRD memory are relatively complex and are not able to effectively generate low-bit-count PRD in standard cell libraries. Accordingly, there is a need for low-bit-count PRD designs and methods for generating PRD memory, such as OTP memory, in standard cell libraries.